MT18LSDT6472DG-13EB2  

参数	数值
规格书	数据手册下载
Total Density	512 MB
Data Bus Width	72 Bit
Package	168RDIMM
Operating Temperature	0 to 70 °C
Number of Chip per Module	18
Sub-Category	SDRAM
Typical Operating Supply Voltage	3.3 V
Chip Density	256 Mb
Main Category	DRAM Module
Maximum Clock Rate	133 MHz
Organization	64Mx72