SN74LV07ADR  

参数	数值
规格书	数据手册下载
Polarity	Non-Inverting
Tolerant I/Os	5 Inputs V
Package	14SOIC
Maximum Propagation Delay Time @ Maximum CL	15.2@2.5V|10.6@3.3V|7.5@5V ns
Logic Function	Buffer/Driver
Logic Family	LV
Input Signal Type	Single-Ended
Output Type	Open Drain
Number of Outputs per Chip	6