SN74AUP3G07YFPR  

参数	数值
规格书	数据手册下载
Polarity	Non-Inverting
Tolerant I/Os	3.6 V
Package	8DSBGA
Maximum Propagation Delay Time @ Maximum CL	14.4@1.2V|12.3@1.5V|9.7@3.3V|6.7@2.5V ns
Logic Function	Buffer/Driver
Logic Family	AUP
Input Signal Type	Single-Ended
Output Type	Open Drain
Number of Outputs per Chip	3