74LVC2G17W6-7  

参数	数值
规格书	数据手册下载
Polarity	Non-Inverting
Tolerant I/Os	5.5 V
Package	6SOT-26
Maximum Propagation Delay Time @ Maximum CL	7.1@3.3V|5.4@5V ns
Logic Function	Schmitt Trigger Buffer
Logic Family	LVC
Input Signal Type	Single-Ended
Number of Outputs per Chip	2