美芯商城为您提供Xilinx生产的IP核产品, IP核
Xilinx生产的IP核产品, IP核共有 55 产品
| 型号 | 生产厂家 | 产品描述 | |
| EF-DI-CTC-80216E-ENC-SITE | Xilinx | 802.16E CTC ENCODER V3.0 IS A PARALLELIZED IMPLEMENTATION OF THE CONVOLUTIONAL TURBO CODER |  |
| EF-DI-DISPLAYPORT-SITE | Xilinx | LOGICORE IP, DISPLAYPORT INTERCONNECT PROTOCOL | |
| EF-DI-EAVB-EPT-SITE | Xilinx | ETHERNET AUDIO VIDEO BRIDGING ENDPOINT | |
| EF-DI-IMG-ENHANCE-SITE | Xilinx | LOGICORE IP, PROVIDES USERS WITH AN EASY TO USE IP BLOCK | |
| EF-DI-IMG-MA-NOISE-SITE | Xilinx | LOGICORE IP MOTION ADAPTIVE NOISE REDUCTION | |
| EF-DI-IMG-NOISE-SITE | Xilinx | LOGICORE IP IMAGE NOISE REDUCTION | |
| EF-DI-IMG-STATS-SITE | Xilinx | LOGICORE IP IMAGE STATISTICS IMPLEMENTS THE COMPUTATIONALLY INTENSIVE METERING FUNCTIONALITY | |
| EF-DI-INTERLEAV-SITE | Xilinx | Interleaver/De-Interleaver IP Core Used In Communication Systems To Overcome Correlated Channel Noise | |
| EF-DI-MIMODEC-LTE-SITE | Xilinx | LOGICORE IP 3GPP LTE MIMO DECODER V1.0 | |
| EF-DI-MIMOENC-LTE-SITE | Xilinx | 3GPP LTE MIMO ENCODER PROVIDES A FLEXIBLE AND HIGHLY OPTIMIZED IMPLEMENTATION OF THE MIMO ENCODING | |
| EF-DI-MOST-SITE | Xilinx | MEDIA ORIENTED SYSTEMS TRANSPORT NETWORK INTERFACE CONTROLLER CORE | |
| EF-DI-OBSAI-SITE | Xilinx | HIGH PERFORMANCE IP CORE IMPLEMENTS AN OBSAI RP3 INTERFACE | |
| EF-DI-OSD-SITE | Xilinx | LOGICORE IP VIDEO ON SCREEN DISPLAY | |
| EF-DI-PC-CFR-SITE | Xilinx | LOGICORE IP PEAK CANCELLATION CREST FACTOR REDUCTION | |
| EF-DI-PCI-AL-SITE | Xilinx | 32 BIT INITIATOR/TARGET V3 AND V4 FOR PCI | |
| EF-DI-PCI32-IP-SITE | Xilinx | 32 BIT INITIATOR/TARGET V3 AND V4 FOR PCI | |
| EF-DI-PCI32-SP-PROJ | Xilinx | 32 BIT INITIATOR/TARGET V3 AND V4 FOR PCI | |
| EF-DI-PCI64-IP-SITE | Xilinx | 64-BIT INITIATOR/TARGET V3 AND V4 FOR PCI | |
| EF-DI-PCIE-PIPE-SITE | Xilinx | ENDPOINT PIPE V1.7 FOR PCI EXPRESS | |
| EF-DI-PCIX-V5-SITE | Xilinx | INITIATOR/TARGET FOR PCI, 64 BIT, 133/66 MHZ INTERFACE WITH 3.3 V OPERATION | |
| EF-DI-PCIX64-VE-SITE | Xilinx | INITIATOR/TARGET FOR PCI, 64 BIT, 133/66 MHZ INTERFACE WITH 3.3 V OPERATION | |
| EF-DI-RACH-3GPP-SITE | Xilinx | 3GPP RACH PREAMBLE DETECTOR PROVIDES AN OPTIMAL SOLUTION | |
| EF-DI-RSD-SITE | Xilinx | HIGH SPEED, COMPACT REED SOLOMON DECODER | |
| EF-DI-RSE-SITE | Xilinx | REED SOLOMON ENCODER IMPLEMENTS MANY DIFFERENT REED SOLOMON CODING STANDARDS | |
| EF-DI-SEARCHER-3GPP-SITE | Xilinx | 3GPP SEARCHER IS A HIGHLY INTEGRATED SOLUTION | |
| EF-DI-TCCDEC-LTE-SITE | Xilinx | 3GPP LTE TURBO DECODER IS USED IN CONJUNCTION WITH A TCC ENCODER | |
| EF-DI-TCCDEC-SITE | Xilinx | TURBO CONVOLUTIONAL CODE DECODER | |
| EF-DI-TCCDEC-UMTS-SITE | Xilinx | UMTS/3GPP TURBO CONVOLUTIONAL DECODER | |
| EF-DI-TCCENC-LTE-SITE | Xilinx | 3GPP LTE TURBO ENCODER IMPLEMENTS THE 3GPP LONG TERM EVOLUTION | |
| EF-DI-TCCENC-SITE | Xilinx | TURBO CONVOLUTIONAL CODE ENCODER | |
| EF-DI-TCCENC-UMTS-SITE | Xilinx | UMTS/3GPP TURBO CONVOLUTIONAL CODE ENCODER | |
| EF-DI-TEMAC-SITE | Xilinx | TRI MODE ETHERNET MEDIA ACCESS CONTROLLER | |
| EF-DI-USB2-DEVICE-SITE | Xilinx | UNIVERSAL SERIAL BUS 2.0 HIGH SPEED DEVICE | |
| EF-DI-VID-DMA-SITE | Xilinx | VIDEO DIRECT MEMORY ACCESS CORE | |
| EF-DI-VID-TIMING-SITE | Xilinx | LOGICORE IP VIDEO TIMING CONTROLLER | |
| EF-DI-VITERBI-SITE | Xilinx | VITERBI DECODER USED FOR FORWARD ERROR CORRECTION APPLICATIONS | |
| EF-DI-RIO-LOG-SITE | Xilinx | Logicore IP Serial Rapidio Endpoint | |
| EF-DI-RIO-PHY-SITE | Xilinx | Logicore IP Serial Rapidio Endpoint | |
| EF-DI-TEMAC-SI> | xilinx | The Xilinx Tri-Mode Ethernet MAC core is a parameterizable core ideally suited for use in networking equipment such as switches and routers. The customizable TE | |
| DO-DI-PCI32-IP | Xilinx | 32-BIT INITIATOR/TARGET V3 AND V4 FOR PCI | |
| DO-DI-PCI64-IP | Xilinx | V3 AND V4 64-BIT VIRTEX AND SPARTAN AND VIRTEX PRODUCT LOUNGE FOR PCI CORES | |
| DO-DI-PCIX64-VE | Xilinx | LOGICORE, 64 BIT INITIATOR/TARGET FOR PCI X | |
| DO-DI-TEMAC | Xilinx | Tri Mode Ethernet MAC That Offers Hard EMAC Blocks And Wrappers | |
| EF-DI-VLYNQ-SITE | Xilinx | INTERFACE CORE FOR COST SENSITIVE APPLICATIONS | |
| EF-DI-POSL4MC-SITE | Xilinx | SPI 4.2 PHASE CORE PROVIDES ULTIMATE FLEXIBILITY WHILE SEAMLESSLY INTEROPERATING | |
| DO-DI-POSL3MC | Xilinx | LogiCORE POS-PHY L3 Link Layer Interface, Multi - Channel | |
| DO-DI-VITERBI | Xilinx | LogiCORE Viterbi Decoder | |
| EF-DI-10-100-EMAC-SITE | Xilinx | OPB ETHERNET MEDIA ACCESS CONTROLLER | |
| EF-DI-10GEMAC-SITE | Xilinx | 10 GIGABIT ETHERNET MAC V9.3 IS A SINGLE SPEED, FULL DUPLEX 10 GBPS ETHERNET | |
| EF-DI-CAN-XA-SITE | Xilinx | CAN IP CORE DESCRIBES THE ARCHITECTURE AND FEATURES OF THE XILINX CAN CONTROLLER CORE | |
